Weekend / Online - Physical Design
StarVLSI offers a 4-month live, online, instructor-led Professional Development Course in PhysicalDesign, providing participants with the opportunity for hands-on experience with Synopsis Tools.The main objective of the course is to reduce the disparity in skills between academic learningand industry demands, acting as a gateway for recent engineering graduates and post-graduates in Electronics, Instrumentation, Electrical, and Telecommunication to enter thedynamic VLSI industry.
Next Batch – TBD
Highly rated on Google
4.9/5
Course Duration
4 months
Learning Mode
Online
Placement's*
100%
Career prospects in Physical Design
The increasing demand for smaller, faster, and more efficient electronicdevices is fueling the necessity for advanced Very Large ScaleIntegration (VLSI) technology. The VLSI field is in a constant state ofevolution, presenting new challenges and opportunities regularly.Salaries in this domain can range from 3 lakhs per annum to 20 lakhsper annum, depending on experience and skill set.
In India, the demand for VLSI engineers remains robust, especially in thesemiconductor and electronic industries. The rising demand forconsumer electronics is anticipated to sustain the need for skilled VLSIengineers, potentially resulting in a salary uptrend in the coming year.
Eligibility Criteria
B.TECH/B.E in Electrical Instrumentation
M.TECH in VLSI
B.Tech/B.E in Electronics and Communication(EEE)
B.Tech/B.E in Electrical and Electronics
Skills you will gain
Floor Planning
Placement
CTS
Routing
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PROGRAM HIGHLIGHTS
- 10+ years industry experience trainers
- Real Time Projects
- Industry Standards Tool
- Module Wise Assignments
- Individual Focus
- Soft Skills Session
- 100% Placement's*
- Mock Interview by Industry Experts Talk
KEY TAKEAWAY
- Industry-ready transformation through training
by Synopsis-certified instructors - Learning from a highly acclaimed trainer with a
track record of successful training deliveries - Hands-on experience in designing, simulating,
and implementing digital circuits - Confidence-building for a career in the
semiconductor industry - 100% Placement’s*
WHO CAN JOIN?
- 2017 to 2024 batch B.E / B.Tech in Electronics
Electrical - Instrumentation Communication
- Telecommunication Engineering
- 2017 and 2024 batch M.Tech / M.S in VLSI
- Embedded Systems
- Electronics Similar
ADMISSION CRITERIA
- Candidates will have to clear an online admission
test and an online interview and screening
process. - Candidate will have to accept in writing, the terms
and - conditions of admission before joining the course.
PROGRAM PRE-REQUISITES
- Candidates must have a laptop/desktop with
minimum configuration: 64-bit processor, 8GB
RAM, 100GB - free space, Minimum 2Mbps broadband
connection and Good quality headphones
TOOLS/HARDWARE/SOFTWARE:
- Fusion Compiler /Synopsis ICC2 - 14nm FinFET
- Prime Time - PT / Design Compiler - DC
- VPN Provided
What you will learn
- Logic Gates
- Boolean Algebras, Boolean Expression and K-Map
- Combinational Circuits: Adders, Subtractors, Multiplexer, Demultiplexer,
- Encoders, Priority Encoder, Decoders, Comparator, and converters.
- Sequential Circuits: Latches, Flip-Flops, Registers and Counters
- Introduction to MOSFET
- CMOS Inverter and its characteristics
- Fabrication Process, Stick Diagrams and Layout Second Order Effects
- Basics
- Terminologies, Types of Network Elements
- Ohm’s law, Resistors, KCL and KVL Assignments Capacitors, Inductors and RC Circuits
- Introduction to LINUX
- basic commands in LINUX
- Sed/Awk hacks
- Vim hacks
1-Introduction to STA
- What is Timing?
- Analysis / Types of STA/ Advantages of STA
2-Inputs and Outputs of STA
3-Terminologies in STA
- Slew, Delay in Circuits
- Setup and Hold time/ Timing arcs/ Problems on slew and delay
4-Timing Path Groups
- Terminologies related to path groups.
- Problems on Path groups
5-Clocks/ Pulse width/ Period/ Frequency/ Duty Cycle/ Edges/ Clock Abnormalities
6- Timing Exceptions
7-PVT conditions, OCV, CRPR and Problems
8-Timing Reports and fixing the timing violations
9-Signal Integrity
1. PD flow
2. Design setup
- Course
- Content
- Library/ DEF/ SPEF/ Netlist/ SDC/ LEF/ UPF
3. Floor planning
- Defining the chip/die/core area
- Placing the pin or IO placement
- Macro placement
- Adding blockages/defining the placement routing blockages
4-Power Planning
5-Placement placement
- Goals for placement optimization
- Intermediate steps in placement optimization
- Analysis and Debug
6-CTS/ Pre-CTS checks/ Goals for CTS/ Post-CTS optimizations
7-Routing
- Global Routing/ Track assignments/ Detail Routing
8- Projects 14NM