1. Logic Gates
2. Boolean Algebras, Boolean Expression and K-Map
3. Combinational Circuits:Adders, Subtractors, Multiplexer, Demultiplexer, Encoders,
   Priority Encoder, Decoders, Comparator, and converters.
4. Sequential Circuits: Latches, Flip-Flops, Registers and Counters
   Module Test and Mock Interview

1. Introduction to MOSFET
2. CMOS Inverter and its characteristics
3. Fabrication Process, Stick Diagrams and Layout
4. Second Order Effects
   Module Test and Mock Interview

1. Basics
2. Terminologies, Types of Network Elements
3. Assignments
4. Ohm’s law, Resistors, KCL and KVL Assignments Capacitors, Inductors and RC Circuits
   Module Test and Mock Interview

1. Introduction to STA
   
   • What is Timing
   • Analysis
   • Types of STA
   • Advantages of STA
2. Inputs and Outputs of STA
3. Terminologies in STA
   • Slew, Delay in Circuits
   • Setup and Hold time
   • Timing arcs
   • Problems on slew and delay
4. Timing Path Groups
   • Terminologies related to path groups
   • Problems on Path groups
5. Clocks
   • Pulse width
   • Period
   • Frequency
   • Duty Cycle
   • Edges
   • Clock Abnormalities
6. Timing Exceptions
7. PVT conditions, OCV, CRPR and Problems
8. Timing Reports and fixing the timing violations

Signal Integrity
Module Test and Mock Interview

1. PD flow
2. Design setup
   • Library
   • DEF
   • SPEF
   • Netlist
   • SDC
   • LEF
   • UPF
3. Floor planning

4. Defining the chip/die/core area

5. Placing the pin or IO placement

6. Macro placement

7. Adding blockages/defining the placement and routing blockages

8. Power Planning

9. Placement
   • Goals for placement optimization
   • Intermediate steps in placement optimization
   • Analysis and Debug
10. CTS
    • Pre-CTS checks
    • Goals for CTS
    • Post-CTS optimizations
11. Routing
    • Global Routing
    • Track assignments
    • Detail Routing

Module test and mock interview