Physical Design
The physical design process produces a set of layout files, which describe the position of cells, and routes for the interconnections between them. The layout is subject to constraints like area, power, and performance. Physical design of ASICs is the process of transforming the circuit description into the physical layout.
Highly rated on Google
4.9/5
Course Duration
4 months
Learning Mode
Offline
Placement
100%
Career prospects in Physical Design
Physical Design Engineer interact with the design team to solve the problems and also to propose new ideas,collaborate with the Design Automation team, to prototype, construct, modify and evaluate semiconductor devices and components.
Eligibility Criteria
B.TECH/B.E in Electrical Instrumentation
M.TECH in VLSI
B.Tech/B.E in Electronics and Communication(EEE)
B.Tech/B.E in Electrical and Electronics
Skills you will gain
Floorplanning
Placement
CTS(Clock Tree Synthesis)
Routing
Sign Off
What you will learn
- Logic Gates
- Boolean Algebras, Boolean Expression and K-Map
- Combinational Circuits:Adders, Subtractors, Multiplexer, Demultiplexer, Encoders,
Priority Encoder, Decoders, Comparator, and converters. - Sequential Circuits: Latches, Flip-Flops, Registers and Counters
Module Test and Mock Interview
- Introduction to MOSFET
- CMOS Inverter and its characteristics
- Fabrication Process, Stick Diagrams and Layout
- Second Order Effects
Module Test and Mock Interview
- Basics
- Terminologies, Types of Network Elements
- Assignments
- Ohm’s law, Resistors, KCL and KVL Assignments Capacitors, Inductors and RC Circuits
Module Test and Mock Interview
- Introduction to STA
- What is Timing
- Analysis
- Types of STA
- Advantages of STA
- Inputs and Outputs of STA
- Terminologies in STA
- Slew, Delay in Circuits
- Setup and Hold time
- Timing arcs
- Problems on slew and delay
- Timing Path Groups
- Terminologies related to path groups
- Problems on Path groups
- Clocks
- Pulse width
- Period
- Frequency
- Duty Cycle
- Edges
- Clock Abnormalities
- Timing Exceptions
- PVT conditions, OCV, CRPR and Problems
- Timing Reports and fixing the timing violations
Signal Integrity
Module Test and Mock Interview
- PD flow
- Design setup
- Library
- DEF
- SPEF
- Netlist
- SDC
- LEF
- UPF
- Floor planning
Defining the chip/die/core area
Placing the pin or IO placement
Macro placement
Adding blockages/defining the placement and routing blockages
Power Planning
- Placement
- Goals for placement optimization
- Intermediate steps in placement optimization
- Analysis and Debug
- CTS
- Pre-CTS checks
- Goals for CTS
- Post-CTS optimizations
- Routing
- Global Routing
- Track assignments
- Detail Routing
Module test and mock interview
Companies hiring PD engineers ->
