1.Which symbol is used for non-blocking assignment?
2.What is the purpose of initial block?
3.Which keyword is used to define a module?
4.What is the default value of an uninitialized reg in simulation?
5.Which operator is used for bitwise AND?
6. What does posedge indicate?
7. Which construct is used for continuous assignment?
8.Which loop is NOT supported in Verilog?
9. Which statement is used for conditional execution?
10. What is the purpose of wire?
11. What is the synthesized hardware for the following code?
always @(a or b)
 y = a & b;
12. What happens if a sensitivity list is incomplete?
13. Identify the issue in the code:
always @(posedge clk)
 q = d;
14. What hardware is inferred?
always @(*)
 if (en)
   y = d;
15. What is the output?
reg [3:0] a = 4'b1010;
reg [3:0] b = 4'b0101;
assign y = a + b;
16. Which construct is synthesizable?
18. What is the issue with this code?
always @(posedge clk or posedge rst)
 if (rst)
   q <= 0;
19.Which type is required for assigning inside always block?
21.What does $clog2(16) return?
22.What happens in this code?
always @(posedge clk)
begin
 a <= b;
 b <= a;
end
23.What is the output width?
assign y = 4'b1111 + 4'b0001;
24.What issue exists here?
always @(*)
begin
 if (sel)
   y = a;
 else if (sel == 0)
   y = b;
end
25.Identify the issue:
assign y = a & b;
always @(posedge clk)
 y <= c;
