Starvlsi

# Logic Design

LOGIC DESIGN is a critical component in embedded interfaces. When we design logic using components that have been designed to work together, we can concentrate on their logical function. But interfacing often requires us to mix and match components, exposing incompatibilities. In these cases, an understanding of the circuit characteristics of logic is essential to ensuring that the logic works as intended.

1).Combinational Logic Circuit.

•  Half-subtractor
• Full-subtractor
• Multipliers
• Decoders
• Encoders
• Priority Encoders
• Comparators

•  Shift registers
•  Counters
•  Finite State Machines
•  Melay Model
•  Moore Model
•  State Encoding Technique
•  One hot coding
•  Binary/Sequential Encoding
•  Gray Encoding
•  Memory
•  Introduction to memory
•  Classification to memory
Static Random Access Memories
FIFO (Operations and Applications)
FIFP depth calculation

3).Delays in Combinational logic circuits

•  Delays in digital circuits
• Propagation Delay in logic gates

4).Delay in sequential Circuits

• Setup and hold time
•  Recovery and Removal time
• Timing closure in ASIC/FPGA design
•  Metastability
• Synchronizer circuits

5).Concept of glitches and hazards in combinational logic circuits

• Static hazards
•  Dynamic hazards

B.TECH/B.E in Electronics and communication(ECE)

or

B.TECH/B.E in Electrical and Electronics(EEE),

or

B.TECH/B.E in Electrical Instrumentation

or

M.TECH in VLSI

and all other related branches.

# RTL Design.

In digital circuit design, Register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.

1).Introduction to digital design using HDLs.

• Explain the needs for HDLs.
• Understand difference between HLLs and HDLs.
•  Illustrate a Register Transfer Level (RTL) design.
• Describe the design entry process in the design flow.

2).Definitions and Commonly terminologies

• Define common terms used by RTL design engineers.
• Use the terminologies to effectively and efficiently
communicate with other design engineers.

3).Verilog Constructs

•  Data types, operators and expressions
• Timing Controls
•  Verilog stratified event queue
•  Verilog module and procedural blocks
•  Loops in Verilog
•  File I/O
• Inertial and Transport delays
• Examples of Testbench used for simulation

4).Inference of Hardware from Verilog code

• Always blocks
Infers both combinational and sequential logic.
• Continuous assignments

5).General coding guidelines for Verilog

• Guidelines for synthesizability
• Guidelines for Re-usability

6). Modelling FSMs and Memories in Verilog

•  Memories
RAM design
FIFO design

7).Deliverables of an RTL design Engineers

• Design for Testability
• Design for low power
• Design should be lint clean
• Design should be CDC clean
• Meet synthesis and timing requirements

B.TECH/B.E in Electronics and communication(ECE)

or

B.TECH/B.E in Electrical and Electronics(EEE),

or

B.TECH/B.E in Electrical Instrumentation

or

M.TECH in VLSI

and all other related branches.

# Design Verification.

The design abstraction of a digital circuit is a logical construct which models a digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. The model is commonly called a register transfer level (RTL) design. In order to test a circuit, the RTL must be verified for every feature

Next Batch Commencing on 28th November,2022 28th November,2022 28th November,2022

1).Introduction to RTL Verification using Verilog

• Introduction to RTL Verification
• Verification planning
•  Testbench Architecture
•  Project Work

2).Introduction to RTL Verification

• Introduction to functional Verification
•  Evolution of RTL Verification process
• Basic Concepts and terminologies
• Introduction to a Testbench
Verification Planning

3).Introduction to verification planning

•  Development of verification plan for
Testbench Architecture
•  Testbench development and simulation
Coverage
• Code Coverage

B.TECH/B.E in Electronics and communication(ECE)

or

B.TECH/B.E in Electrical and Electronics(EEE),

or

B.TECH/B.E in Electrical Instrumentation

or

M.TECH in VLSI

and all other related branches.

# Synthesis.

Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates.

1).Input files

• Libraries
• HDL
• Constraints

2).Synthesis Flow

• RTL Optimization
• Logical Optimization
• Gate Level Optimization

3).Analyzing and Debugging Timings

4).Report Generation.

B.TECH/B.E in Electronics and communication(ECE)

or

B.TECH/B.E in Electrical and Electronics(EEE),

or

B.TECH/B.E in Electrical Instrumentation

or

M.TECH in VLSI

and all other related branches.