1).Introduction to digital design using HDLs.
- Explain the needs for HDLs.
- Understand difference between HLLs and HDLs.
- Illustrate a Register Transfer Level (RTL) design.
- Describe the design entry process in the design flow.
2).Definitions and Commonly terminologies
- Define common terms used by RTL design engineers.
- Use the terminologies to effectively and efficiently
communicate with other design engineers.
- Data types, operators and expressions
- Timing Controls
- Verilog stratified event queue
- Verilog module and procedural blocks
- Loops in Verilog
- Tasks and Functions
- File I/O
- Inertial and Transport delays
- Examples of Testbench used for simulation
4).Inference of Hardware from Verilog code
- Always blocks
Infers both combinational and sequential logic.
- Continuous assignments
5).General coding guidelines for Verilog
- Guidelines for synthesizability
- Guidelines for Re-usability
6). Modelling FSMs and Memories in Verilog
7).Deliverables of an RTL design Engineers
- Design for Testability
- Design for low power
- Design should be lint clean
- Design should be CDC clean
- Meet synthesis and timing requirements