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What is DFT? Why do we need it?

A simple answer is DFT is a technique, which facilitates a design to become testable after production.

It's the extra logic which we put in the normal design, during the design process, which
helps its post-production testing. Post-production testing is necessary because, the process of
manufacturing is not 100% error free.

There are defects in silicon which contribute towards the
errors introduced in the physical device. Of course a chip will not work as per the specifications
if there are any errors introduced in the production process. But the question is how to detect
that. Since, to run all the functional tests on each of say a million physical devices produced or
manufactured, is very time consuming, there was a need to device some method, which can
make us believe without running full exhaustive tests on the physical device, that the device has
been manufactured correctly. DFT is the answer for that.
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INTRODUCTION  BASICS OF DFT

  • Basics of DLD
  •  Overall VLSI flow
  • History, need and introduction to DFT
  •  DFT Flow at high level
  •  Hardware elements : PLL, Divider, Clock gater, Latch, TDR
  •  Defect, Fault, Fault modelling & Error difference
  • Timing and its role in DFT
  • Basic UNIX commands

SCAN INSERTION:

  • Intro : Basic flow and Architecture
  •  Scan insertion types
          Internal Scan
         Boundary Scan
  •  Scan methodology
  •  Choosing parameters
  •  Chain balancing
  •  Library cells
  •  Types of scanned Flip-flops
        MUX-D
        LSSD
  •  Clock and edge mixing
  •  DFT rules check
  • Scan input and output files
  • Scan Chain re-ordering
  •  Common issues in Scan insertion

SCAN COMPRESSION ( EDT)

  • Need for Compression
  •  Compressor
  •  Decompressor
        Ring oscillator
        Phase shifter
  •  LFSR,LFSM
  •  Compression ratio
  •  Masking logic
  • Internal scan chains
  • Adding sub chains
  • Scan chain Re-order
  • EDT control signals
  • EDT clock and EDT update
  • EDT bypass logic
  • EDT lockup- latch/Terminal lockup-latch
  • Compression ratio
  • Faults inside EDT

ATPG INTRODUCTION

  • What is ATPG?
  •  Basic flow – inputs, process and outputs
  •  Sequential depth
  • Fault models – Stuck, Transition and path delay
  • Fault identification/sensitization
  •  Fault propagation and justification
  •  Fault categories
  • Test procedures
  •  LOS vs LOC
  •  Coverage – Test and fault coverage
  • Coverage Debug
  •  SDC in ATPG
  •  Test time and test volume
  •  Fault grading
  •  SDC delivery for DFT modes

OCC

  • What is OCC
        Advantages
        Disadvantages
  •  Internal    structure of OCC

SIMULATIONS

  • Simulations introduction and why we need
  •  Simulation flow
  •  Tools for simulation
  •  Simulations types
       Serial simulations

         Parallel simulations

  •  Scan simulation debugging
  •  Chain simulation debugging
  •  Timing & no timing simulations with differences?

 Patten failure debugging with simulation and

ATPG

  • Misc
  •  Intro to MBIST
  •  Intro to 1149.1 and TAP
  •  Intro to Bscan
  • Intro to LBIST
  • Intro to diagnosis
  •  Conclusion

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