Frontend Design Verification
The design abstraction of a digital circuit is a logical construct which models a digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. The model is commonly called a register transfer level (RTL) design. In order to test a circuit, the RTL must be verified for every feature.
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Course Duration
4 months
Learning Mode
Offline
Placement
100%
Career prospects in Design Verification
Verification of design is one of the most complicated tasks in today’s design cycle due to the complexity of the design. Approximately, 50-80% of the project time goes into verification of the design.
Eligibility Criteria
B.TECH/B.E in Electrical Instrumentation
M.TECH in VLSI
B.Tech/B.E in Electronics and Communication(EEE)
B.Tech/B.E in Electrical and Electronics
Skills you will gain
SV
System Verilog
SOC
UVM
What you will learn
Logic Design
Half adders,Full adders,Multi-bit Carry ripple adder,Half-subtractor,Full-subtractor,Multipliers,Decoders,Encoders,Priority Encoders,Comparators,Code Converters
- Shift registers
- Counters
- Finite state machines
- Melay model
- Moore model
- State encoding technique
- One hot coding
- Binary/Sequential Encoding
- Gray Encoding
- Memory
- Introduction to memory
- Classification to memory
- Static random access memories
- FIFO(Operations and Applications)
- FIFP depth calculation
- Delays in logical circuits
- Propogation delay in logic gates
- Setup and hold time
- Recovery and Removal time
- Timing closure in ASIC/FPGA design
- Metastability
- Synchronizer circuits
- Static Hazards
- Dynamic Hazards
RTL Design
- Explain the needs for HDLs.
- Understand difference between HLLs and HDLs.
- Illustrate a Register Transfer Level (RTL) design.
- Describe the design entry process in the design flow.
- Define common terms used by RTL design engineers.
- Use the terminologies to effectively and efficiently communicate with other design engineers.
- Data types, operators and expressions
- Timing Controls
- Verilog stratified event queue
- Verilog module and procedural blocks
- Loops in Verilog
- Tasks and Functions
- File I/O
- Inertial and Transport delays
- Examples of Testbench used for simulation
- Always blocks
- Infers both combinational and sequential logic.
- Continuous assignments
- Guidelines for synthesizability
- Guidelines for Re-usability
- Memories
- RAM design
- FIFO design
- Design for Testability
- Design for low power
- Design should be lint clean
- Design should be CDC clean
- Meet synthesis and timing requirements
RTL Verification
- Introduction to RTL Verification
- Verification planning
- Testbench Architecture
- Advances in RTL Verification
- Project Work
- Introduction to functional Verification
- Evolution of RTL
- Verification process
- Basic Concepts and terminologies
- Introduction to a Testbench
- Introduction to verification planning
- Development of verification plan
- Testbench development and simulation
- Code Coverage
- Introduction to SV.
- Commonly used terminologies in SV.
- Data Types
Object-Oriented Programming (OOP) concepts - SV stratified event queue/schedule
- SV Task and functions
- Verification specific SV constructs.
- Functional coverages
- Verification planed and SV Testbench Architecture
- Modelling Testbench blocks
- Assertions Based Verification
- Introduction UVM
- Commonly used Terminology in UVM
- Testbench structure
- Overview of project
- UVM Testbench Architecture
- Creating UVCs and Environment
- Configuring Testbench environment
- UVM sequence
- UVM sequencer
- Virtual sequence and sequencer
- Callback
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