Frontend Design Verification

The design abstraction of a digital circuit is a logical construct which models a digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. The model is commonly called a register transfer level (RTL) design. In order to test a circuit, the RTL must be verified for every feature.

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Course Duration

4 months

Learning Mode




Career prospects in Design Verification

Verification of design is one of the most complicated tasks in today’s design cycle due to the complexity of the design. Approximately, 50-80% of the project time goes into verification of the design.

Eligibility Criteria

B.TECH/B.E in Electrical Instrumentation


B.Tech/B.E in Electronics and Communication(EEE)

B.Tech/B.E in Electrical and Electronics

Skills you will gain


System Verilog



What you will learn

Logic Design

Half adders,Full adders,Multi-bit Carry ripple adder,Half-subtractor,Full-subtractor,Multipliers,Decoders,Encoders,Priority Encoders,Comparators,Code Converters

  1. Shift registers
  2. Counters
  3. Finite state machines
    • Melay model
    • Moore model
  4. State encoding technique
    • One hot coding
    • Binary/Sequential Encoding
    • Gray Encoding
  5. Memory
    • Introduction to memory
    • Classification to memory
      • Static random access memories
      • FIFO(Operations and Applications)
      • FIFP depth calculation
  1. Delays in logical circuits
  2. Propogation delay in logic gates
  1.  Setup and hold time
  2. Recovery and Removal time
  3. Timing closure in ASIC/FPGA design
  4. Metastability
  5. Synchronizer circuits

RTL Design

  1. Explain the needs for HDLs.
  2. Understand difference between HLLs and HDLs.
  3. Illustrate a Register Transfer Level (RTL) design.
  4. Describe the design entry process in the design flow.
  1. Define common terms used by RTL design engineers.
  2. Use the terminologies to effectively and efficiently communicate with other design engineers.
  1. Data types, operators and expressions
  2. Timing Controls
  3. Verilog stratified event queue
  4. Verilog module and procedural blocks
  5. Loops in Verilog
  6. Tasks and Functions
  7.  File I/O
  8. Inertial and Transport delays
  9. Examples of Testbench used for simulation
  1. Always blocks
  2. Infers both combinational and sequential logic.
  3. Continuous assignments
  1. Guidelines for synthesizability
  2. Guidelines for Re-usability
  1. Memories
    • RAM design
    • FIFO design
  1. Design for Testability
  2. Design for low power
  3. Design should be lint clean
  4. Design should be CDC clean
  5. Meet synthesis and timing requirements

RTL Verification

  1. Introduction to RTL Verification
  2. Verification planning
  3. Testbench Architecture
  4. Advances in RTL Verification
  5. Project Work
  1.  Introduction to functional Verification
  2. Evolution of RTL
  3. Verification process
  4. Basic Concepts and terminologies
  5. Introduction to a Testbench
  1. Introduction to verification planning
  2. Development of verification plan
  1. Testbench development and simulation
  1. Code Coverage
  1. Introduction to SV.
  2. Commonly used terminologies in SV.
  3. Data Types
    Object-Oriented Programming (OOP) concepts
  4. SV stratified event queue/schedule
  5. SV Task and functions
  6. Verification specific SV constructs.
  7. Functional coverages
  8. Verification planed and SV Testbench Architecture
  9. Modelling Testbench blocks
  10. Assertions Based Verification
  1. Introduction UVM
  2. Commonly used Terminology in UVM
  3. Testbench structure
  4. Overview of project
  5. UVM Testbench Architecture
  6. Creating UVCs and Environment
  7. Configuring Testbench environment
  8. UVM sequence
  9. UVM sequencer
  10. Virtual sequence and sequencer
  11. Callback

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