Frontend Design Verification

The design abstraction of a digital circuit is a logical construct which models a digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. The model is commonly called a register transfer level (RTL) design. In order to test a circuit, the RTL must be verified for every feature.

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Course Duration

4 months

Learning Mode




Career prospects in Design Verification

Verification of design is one of the most complicated tasks in today’s design cycle due to the complexity of the design. Approximately, 50-80% of the project time goes into verification of the design.

Eligibility Criteria

B.TECH/B.E in Electrical Instrumentation


B.Tech/B.E in Electronics and Communication(EEE)

B.Tech/B.E in Electrical and Electronics

Skills you will gain


System Verilog



What you will learn


System Verilog


AMBA Protocols

  • what are the drawbacks of the Higher Level Language
  • Why Hardware Descritor Language HDL ?
  • Module introdcution
  • Structure of modules
  • What is 2 state and 4 state variables
  • Different data types
  • Differnet ways of mentioing comments
  • Verilog Number specification
  • Parameters and Parameter overriding
  • Module instances
  • proceddural statements
  • Connectivity in verilog
  • Port assignments
  • Different level of abstractions
  • Generate statemntes
  • Delays in verilog
  • Introdcution to Verilog Test Bench
  • Blocking and non-Blocking assingmnet
  • Sequental circuit implementation in verilog
  • Procedural and concurrent assignments
  • system tasks
  • Verilog scheduling
  • Race condition in verilog
  • why all the codes can't be used for ASIC design
  • why to follow the IEEE standard in coding ?
  • How to design the system using Moore and Melay Machines
  • Difference between Moore and Melay machine
  • States in FSM coding
  • RTL coding using Melay and
  • Moore machines using different technique
  • Developing the TB for FSM RTL
  • Built-In Data Types
  • Fixed-Size Arrays
  • Dynamic Arrays
  • Queues
  • Associative Arrays
  • Array Methods
  • Packages
  • Streaming Operators
  • Enumerated Types
  • Strings
  • Constant
  • Tasks, Functions, and Void Functions
  • Task and Function Overview
  • Routine Arguments
  • Local Data Storage
  • Time Values
  • Separating the Testbench and Design
  • The Interface Construct
  • Stimulus Timing
  • Creating New Objects
  • Separating the Declaration and Construction
  • Getting a Handle on Objects
  • Defining Methods Outside of the Class
  • Static Variables vs. Global Variables
  • Scoping Rules
  • Understanding Dynamic Objects
  • Copying Objects
  • What to Randomize
  • Randomization in SystemVerilog
  • Constraint Details
  • Controlling Multiple Constraint Blocks
  • Implication and Bidirectional Constraints
  • Valid Constraints
  • In-Line Constraints
  • The pre-randomize and post-randomize Functions
  • Note on Void Functions
  • Turn Constraints Off and On
  • Checking Values Using Constraints
  • Common Randomization Problems
  • Iterative and Array Constraints
  • Random Control
  • Using fork join and begin end
  • Spawning Threads with fork join none
  • Synchronizing Threads with fork join any
  • Creating Threads in a Class
  • Dynamic Threads
  • Waiting for all Spawned Threads
  • Disabling Threads
  • Interprocess Communication
  • Events
  • Semaphores
  • Mailboxes
  • Building a Testbench with
  • Threads and IPC
  • Introduction to Inheritance
  • Downcasting and Virtual Methods
  • Composition, Inheritance, and Alternatives
  • Copying an Object
  • Abstract Classes and Pure Virtual
  • Methods
  • Callbacks
  • Parameterized Classes
  • Static and Singleton Classes
  • Coverage Types
  • Functional Coverage Strategies
  • Simple Functional Coverage
  • Anatomy of a Cover Group
  • Triggering a Cover Group
  • User-Defined Bins
  • Default Bins
  • Wildcard Bins
  • cross coverage
  • Ignore and Illegal Bins
  • Introductionto interface
  • Need of interface
  • Parameterized Interfaces and Virtual Interfaces
  • Advantes and need of interface
  • Need of assertion
  • Immediate assertion
  • Concurrent assertion
  • Cycle delays in assertion
  • How to write the assertions for APB protocol
  • Understanding the drawback of SV
  • Evolution of Methodology
  • UVM evolution
  • Benefits of using UVM
  • UVM class Hierarchy
  • UVM Transaction Data Sequence Item, Sequence, Virtual Sequence
  • UVM Testbench component - Driver, Sequencer, Monitor, Agent, Virtual sequencer, Envirnoment, Test
  • UVM Message format
  • UVM message Verbosity
  • TLM Communication - How TLM are used to communicate between components
  • TLM Analysis port
  • TLM terminology Put, get, tlm_fifo
  • What are the factories can generate
  • How do you use the factory
  • How to register the components Types with the factory
  • UVM Factory override - set type override by type and set inst override bytype
  • How configuration data base is used
  • Raising and dropping the objection
  • How to create the components using the create method
  • What is the need of phases in factory
  • Common UVM Phases
  • What are objects, what is difference between objects and components
  • How to write the sequences
  • Running the sequences on sequencers
  • Strcuture of the sequence
  • Virtual sequences
  • What is a Sequencers
  • How driver and sequencer commuicate using TLM
  • Flow control Driver - Sequencer- Sequence
  • Virtual sequencers
  • How to create the different components
  • Connecting the differtent components
  • How to create the agent and envirnoment
  • How to use the env in the test case
  • Starting the sequence on sequencers
  • UVM macros
  • UVM call backs
  • APB protocol 3 Hours
  • AHB protocol 8 Hours
  • AXI protocol 12 Hours

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